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19-0729; Rev 0; 1/07
PECI-to-I2C Translator
General Description
The MAX6621 PECI-to-I2C translator provides an efficient, low-cost solution for PECI-to-SMBusTM/I2C protocol conversion. The PECI-compliant host reads temperature data directly from up to four PECI-enabled CPUs. Interrupts are generated when the measured temperature exceeds the high-temperature limit and causes ALERT to assert. The RESET input allows the host to reset the I2C bus in the event of a communication error. The I2C interface provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. This interface allows a maximum serial-data rate of 400kbps. The MAX6621 is designed to operate from a +3.0V to +3.6V supply voltage and ambient temperature range of -20C to +120C.
Features
400kbps I2C-Compatible, 2-Wire Serial Interface +3V to +3.6V Supply Voltage PECI-Compliant Port PECI-to-I2C Translation ALERT Output RESET Input (May Be Disabled as a Factory Option) Programmable Temperature Offsets -20C to +120C Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus Lockup Timeout Reset Lead-Free, 10-Pin MAX(R) Package
MAX6621
Applications
Servers Workstations Desktop Computers
PART MAX6621AUB+ MAX6621AUB+T
Ordering Information
TEMP RANGE -20C to +120C -20C to +120C PIN-PACKAGE 10 MAX 10 MAX
T = Tape-and-reel package. +Denotes a lead-free package.
SMBus is a trademark of Intel Corp. MAX is a registered trademark of Maxim Integrated Products, Inc. Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V VCPU VTT VCC SDA I2 C MASTER RESET ALERT AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR
MAX6621
PECI
________________________________________________________________ Maxim Integrated Products
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PECI-to-I2C Translator MAX6621
ABSOLUTE MAXIMUM RATINGS
(All voltages with respect to GND.) VCC ..........................................................................-0.3V to +4V AD0, RESET, ALERT...................................-0.3V to (VCC + 0.3V) SCL, SDA .................................................................-0.3V to +6V VREF .........................................................................-0.3V to +4V PECI .........................................................-0.3V to (VREF + 0.3V) DC Current through SDA ...................................................10mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C over TA = +70C)......444mW Operating Temperature Range .........................-20C to +120C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = +3V to +3.6V, VREF = +0.95V to +1.26V, TA = -20C to +120C, unless otherwise noted. Typical values are at VCC = +3.3V, VREF = +1.0V, TA = +25C.) (Note 1)
PARAMETER SUPPLY Operating Supply Voltage Operating Supply Current Power-On-Reset Voltage INPUT SCL, INPUT/OUTPUT SDA Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage Leakage Current Input Capacitance ALERT Low-Level Output Voltage ADDRESS INPUT A0/RST Low-Level Input Voltage High-Level Input Voltage Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input Voltage Range Low-Level Input Voltage Threshold High-Level Input Voltage Threshold VREF VIN VIL VIH 0.95 -0.3 0.275 x VREF 0.550 x VREF 1.26 VREF + 0.3 0.500 x VREF 0.725 x VREF V V V V VIL VIH IL CI 0.7 x VCC -2 10 0.3 x VCC VCC + 0.3 +2 V V A pF VOL IOL = 6mA 0.4 V VIL VIH VOL IL CI IOL = 6mA -1 10 0.7 x VCC 0.3 x VCC 5.5 0.4 +1 V V V A pF VCC ICC VPOR SCL = 400kHz 2.60 3.0 4 3.6 7 2.95 V mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
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PECI-to-I2C Translator
ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VCC = +3V to +3.6V, VREF = +0.95V to +1.26V, TA = -20C to +120C, unless otherwise noted. Typical values are at VCC = +3.3V, VREF = +1.0V, TA = +25C.) (Note 1)
PARAMETER Hysteresis Low-Level Sinking Current High-Level Sourcing Current Input Capacitance Signal-Noise Immunity Above 300MHz SYMBOL VH IIL IIH CI VN (Note 2) (Note 2) 0.1 x VREF CONDITIONS MIN 0.1 x VREF 0.5 -6 10 1.0 TYP MAX UNITS V mA mA pF VP-P
MAX6621
TIMING CHARACTERISTICS
(Typical Application Circuit, VCC = +3V to +3.6V, VREF = +0.95V to +1.26V, TA = -20C to +120C, unless otherwise noted. Typical values are at VCC = +3.3V, VREF = +1.0V, TA = +25C.) (Note 2)
PARAMETER RESET Pulse Width I2C INTERFACE Serial-Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock-Low Period SCL Clock-High Period Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line PECI INTERFACE Bit Time (Note 7) tBIT Overall time evident on PECI Driven by MAX6621 0.495 0.495 500 250 s fSCL tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tLOW tHIGH tR tF tF.TX tSP Cb (Notes 4, 5) (Notes 4, 5) (Notes 4, 5) (Note 6) (Note 4) 50 (Note 3) 120 1.3 0.6 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 160 400 300 300 250 1.3 0.6 0.6 0.6 0.9 400 kHz s s s s s ns s s ns ns ns ns pF SYMBOL RST CONDITIONS MIN 100 TYP MAX UNITS ns
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PECI-to-I2C Translator MAX6621
TIMING CHARACTERISTICS (continued)
(Typical Application Circuit, VCC = +3V to +3.6V, VREF = +0.95V to +1.26V, TA = -20C to +120C, unless otherwise noted. Typical values are at VCC = +3.3V, VREF = +1.0V, TA = +25C.) (Note 2)
PARAMETER Bit Time Jitter SYMBOL tBIT, jitter CONDITIONS Between adjacent bits in an PECI message header or data bytes after timing has been negotiated Across a PECI address or PECI message bits as driven by MAX6621 (Note 8) 0.6 0.2 0 Measured from VOL to VPMAX, VREF(nom) -5% (Note 9) Measured from VOH to VNMAX, VREF(nom) +5% (Note 9) Time for client to maintain a low idle drive after MAX6621 begins a message (Note 10) A constant low level driven by MAX6621 (Notes 8, 11) From the end of a ResetDevice command to the next message to which the reset client must be able to respond If the prior tBIT is not known by MAX6621, the maximum tBIT must be assumed and tSETUP = 1ms in this case (Note 12) 2 MIN TYP 1 MAX UNITS %
Change in Bit Time High-Level Time for Logic-High High-Level Time for Logic-Low Client Asserts PECI High During Logic-High Rise Time Fall Time Hold Time Stop Time Maximum Dwell Time of the PECI Client
tBIT, drift tH1 tH0 tSU tR tF tHOLD tSTOP
2 0.75 0.3 0.8 0.4 0.2 30 + 5/Node 30/Node 0.5
% x tBIT x tBIT x tBIT-M ns ns x tBIT-1 x tBIT-M
tRESET
0.4
ms
Minimum PECI Low Time Preceding a Message
tSETUP
2
x tBIT-X
Note 1: All parameters are tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design; not production tested. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VCC and 0.7 x VCC. Note 5: ISINK 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VCC and 0.7 x VCC. Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 7: The MAX6621 must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the minimum time less than 500s. tBIT limits apply equally to tBIT-A and tBIT-M. Note 8: The minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse. Note 9: Extended trace lengths can appear as additional nodes. Note 10: The client may deassert its low idle drive prior to the falling edge of the first bit of the message by using the rising edge to detect a message start. However, the time delay must be sufficient to qualify the rising edge as a true message rather than a noise spike. Note 11: The message stop is defined by two consecutive periods when the bus has no rising edge. Tolerance around this time is based on the tBIT-M error budget. Note 12: tSETUP is not additive with tSTOP. Rather, these times may overlap.
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PECI-to-I2C Translator
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME PECI AGND AD0 SDA SCL VCC GND RESET ALERT VREF Analog Ground I2C Bus Device Address Selection Input I2C Bus Data Input/Output I2C Bus Clock Input/Output Power Supply. Bypass to GND with a 0.1F capacitor. Power-Supply Ground I2C Reset Input. Pull RESET low to reset I2C interface and default all registers to startup values. Drive high for normal operation. ALERT Interrupt Open-Drain Output. Asserts low when any temperature exceeds the programmed limit. PECI Input Supply Voltage. Bypass VREF to AGND with a 0.1F capacitor. FUNCTION Platform Environment Control Interface (PECI) Serial-Bus Input/Output
MAX6621
Block Diagram
MAX6621
SDA I 2C PORT SCL
RESET ALERT PECI TRANSLATION ENGINE A0
PECI
PECI PORT
VREF
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PECI-to-I2C Translator MAX6621
Detailed Description
The MAX6621 obtains temperature data from an internal temperature sensor in PECI-compliant hosts. Up to four PECI hosts can be connected to the PECI I/O interface. The MAX6621 handles all the PECI transmissions
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h DESCRIPTION Read socket 0, domain 0 temperature register Read socket 0, domain 1 temperature register Read socket 1, domain 0 temperature register Read socket 1, domain 1 temperature register Read socket 2, domain 0 temperature register Read socket 2, domain 1 temperature register Read socket 3, domain 0 temperature register Read socket 3, domain 1 temperature register Read maximum temperature for all enabled sockets/domains register Read firmware version register Read maximum temperature address Read socket and domain that caused alert Read/write CONFIG0 register Read/write CONFIG1 register Read/write CONFIG2 register Read/write CONFIG3 register Read/write alert temperature for socket 0 Read/write alert temperature for socket 1 Read/write alert temperature for socket 2 Read/write alert temperature for socket 3 Request polling Clear alert
and uses a 2-wire, I2C-compatible serial interface to communicate with the PECI host.
Registers and Commands
The following is an overview of the I2C/SMBus registers/commands supported by the MAX6621.
TRANSACTION TYPE ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord SendByte SendByte
Configuration
The MAX6621 has four configuration registers (Table 1). CONFIG0 is the main configuration register that enables the PECI sockets, I2C bus timeout, PEC, alert activation, and polling delay. CONFIG1 sets the number of retries,
CONFIG2 sets the temperature offset, and CONFIG3 controls the temperature averaging. You can write to the configuration registers to set the configuration or read from the configuration registers to get the current settings.
Table 1. Configuration Registers
COMMAND BYTE 0Ch 0Dh 0Eh 0Fh REGISTER DESCRIPTION CONFIG0 register CONFIG1 register CONFIG2 register CONFIG3 register TYPE ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord ReadWord/WriteWord RESULT See the CONFIG0 section. See the CONFIG1 section. See the CONFIG2 section. See the CONFIG3 section.
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PECI-to-I2C Translator
CONFIG0 The CONFIG0 register holds a bit mask for sockets and domains that are enabled for polling as well as a polling delay (minimum delay between sets of polls) and features enable/disable bits. Table 2 shows the various options for CONFIG0.
The optional polling delay (bits 2:0) inserts after polling the set of all sockets and domains that are enabled in bits 15:8 with a minimal pause of 2.5ms between PECI reads. After polling all enabled sockets and domains, the device pauses PECI communications for the configured time before starting to poll the set of enabled sockets and domains again. Table 3 shows the various polling delay options.
MAX6621
Table 2. CONFIG0 Register
BIT(S) 15:8 15 14 13 12 11 10 9 8 7 6 DESCRIPTION Polling enable for sockets and domains 1 = enable socket 3, domain 1 1 = enable socket 3, domain 0 1 = enable socket 2, domain 1 1 = enable socket 2, domain 0 1 = enable socket 1, domain 1 1 = enable socket 1, domain 0 1 = enable socket 0, domain 1 1 = enable socket 0, domain 0 1 = enable I2C bus lockup timeout 0 = disable timeout 1 = alternate data representation 0 = 16-bit data representation 1 = enable I2C packet error checksum (PEC) on device return data 0 = disable PEC 1 = mask temperature alerts 0 = activate alerts Reserved, set to 0 Poll delay, see Table 3 DEFAULT 00h 0 0 0 0 0 0 0 0 1 0
Table 3. Polling Delay
POLL DELAY VALUE 0 1 2 3 4 5 6 7 DELAY BETWEEN POLLS (ms) Polling on request only 2.5 5 10 50 100 (default) 500 Reserved
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1
CONFIG1 The CONFIG1 register configures the maximum number of retries before aborting a PECI temperature read as well as the originated (suggested) PECI bit time. Table 4 shows the various options for CONFIG1.
Table 4. CONFIG1 Register
0 0 5 15:8 BIT(S) DESCRIPTION Originated PECI bit time (before negotiation) 01h: RESERVED 02h...0FFh: CONFIG1[15:8] + 1s Minimum: 02h (= 3s / 333.3kHz) Maximum: 0FFh (= 256s / 3.906kHz) Maximum number of retries for PECI transactions DEFAULT
4 3 2:0
02h
7:0
03h
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PECI-to-I2C Translator
CONFIG2 The CONFIG2 register holds the offset that is added to all temperature return values that are not error codes. The offset is enabled in CONFIG0, bit 6; +95C is set as 17C0h or 005Fh, depending on the data format. To represent +95C in 16-bit representation, convert +95C to binary using two's complement and left-shift six times. The MAX6621 automatically converts the offset value to the equivalent value when the data format is changed. See Table 5 for the default offset and Table 6 for some example values.
MAX6621
Temperature Representation
Temperature data is formatted in 16-bit two's complement representing a range from -512C to +512C in steps of 1/64C (Figure 1). Internally, the device always uses the 16-bit data format. The temperature is given in two's complement and left-shifted so that the +1C bit is bit 6 (Figure 2). Temperatures can be represented externally in alternate data format if fractional readings are not needed. Table 8 shows some examples.
Table 5. CONFIG2 Register
BIT(S) 15:0 DESCRIPTION Temperature offset DEFAULT 0000h
RESLO 7 6
1 C 2
1 C 8
1 C 32
5
4
3
2
1
0
Table 6. Example Offset Values in 16-Bit Temperature Representation
TEMP (C) 0 +25 +50 +75 +95 HEX 0000h 0640h 0C80h 12C0h 17C0h BINARY RESHI 0000 0000 0000 0110 0000 1100 0001 0010 0001 0111 RESLO 0000 0000 0100 0000 1000 0000 1100 0000 1100 0000
1C
1 C 4
1 C 16
1 C 64
Figure 1. Temperature Measured in 1/64C Steps
-50C
TWO'S COMPLEMENT
1100
1110
When configured in CONFIG2, and the return code is not an error code (see the Error Codes section), the device adds the offset value stored in CONFIG2 to the return value. For example, if the CPU's thermal control circuit activation point is at +95C, CONFIG2 can be set to +95C (005Fh or 17C0h) and all return values are converted to absolute temperatures. Note that the thermal control circuit activation point is CPU specific. The offset value is represented in the current data format.
15 14 13 12 11 10 RESHI
9
8
7 RESLO
6
5
4
3
2
1
0
Figure 2. Conversion of Temperature Done in Two's Complement
CONFIG3 CONFIG3 register configures the temperature averaging function. See the Temperature Averaging section for more information. Table 7 shows the default settings.
Table 8. Example 16-Bit Representation with No Offset (Activation Point = +95C)
TEMP (C) RELATIVE TEMP (C) -1 -10 -25 -50 -75 HEX FFC0h FD80h FDC0h F380h ED30h BINARY RESHI 1111 1111 1111 1101 1111 1101 1111 0011 1110 1101 RESLO 1100 0000 1000 0000 1100 0000 1000 0000 0100 0000
Table 7. CONFIG3 Register
BIT(S) 15:8 7:0 DESCRIPTION Reserved, set to 0 Averaging shift count, see formula DEFAULT 00h 00h
+94 +85 +70 +45 +20
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PECI-to-I2C Translator
Alternate Temperature Value Representation This optional feature can be enabled using bit 6 of CONFIG0. When the alternate data format is enabled, the temperature value is shifted right as shown in Table 9. The most significant bits are set to all 0s or all 1s depending on the sign bit 15, also shown as S in Figure 3. Table 10 shows some example values. This translation is not performed for error codes (16-bit values from 8000h through 81FFh). Excluding error codes, the software only has to examine the RESLO data byte, as it represents an integer value in the range from -128C to +127C in 1C steps. The RESHI byte is all 0s or all 1s for valid return codes, and either 80h or 81h for all error codes. Temperature Averaging The MAX6621 can average several temperature readings and return a value as calculated by:
TNEW = 1 1 x TPECI + 1 - x TOLD 2CONFIG3 2CONFIG3
MAX6621
where TOLD is the previously stored temperature, TPECI is the new value read from PECI, and TNEW is the newly stored temperature ready to be returned through I2C. This calculation can cause significant bits to be lost. Enable temperature averaging by writing the desired averaging amount to the CONFIG3 register. Writing 00h to the CONFIG3 register disables temperature averaging.
FRACTIONAL VALUE RESHI RESLO X 12 11 10 9 8 7 6 X X X X X X S X
Table 9. Alternate Temperature Representation
DESCRIPTION 16-bit value Alternate representation RESHI 15:14:13:12:11:10:9:8 RESLO 7:6:5:4:3:2:1:0
S
S
S
S
S
S
S
S
S
12
11
10
9
8
7
6
15:15:15:15:15:15:15:15 15:12:11:10:9:8:7:6
(SIGN BITS)
INTEGER VALUE (~ 1C)
Figure 3. Alternate Temperature Representation
Table 10. Example Alternate Representation with No Offset (Activation Point = +95C)
TEMP (C) +94 +85 +70 +45 +20 RELATIVE TEMP (C) -1 -10 -25 -50 -75 HEX FFFFh FFF6h FFE7h FFCEh FFB5h BINARY RESHI 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 RESLO 1111 1111 1111 0110 1110 0111 1100 1110 1011 0101
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PECI-to-I2C Translator MAX6621
Temperature Commands
Table 11 shows the different commands for selecting one of the PECI hosts or getting the maximum temperature. Read commands are initiated by the MAX6621, and the result returned is a 16-bit word with the least significant bit (LSB) clocked in first for the selected PECI host. The result consists of RESLO for the 8 LSBs and RESHI for the 8 MSBs, resulting in a 16-bit word. The 16-bit words are temperature values read from the PECI interface. PECI-enabled Intel microprocessors return temperature data in fractions of 1C below the thermal-control-circuit activation point, resulting in negative return values that do not represent absolute temperatures. Absolute temperatures can be achieved by setting the temperature offset in CONFIG2. Table 12 shows example return values for an Intel CPU. Note that the MAX6621 does not interpret the return
Table 11. Read Temperature
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h Socket 0, domain 0 Socket 0, domain 1 Socket 1, domain 0 Socket 1, domain 1 Socket 2, domain 0 Socket 2, domain 1 Socket 3, domain 0 Socket 3, domain 1 Read maximum temperature for all enabled sockets/domains ReadWord 16-bit words REGISTER TYPE RESULT
Table 12. Return Temperature Values
RELATIVE TEMPERATURE (C) -1 -36 -37 -38 -39 -40 -41 -42 -43 CONFIG2 16 BITS 0000 17C0 0000 17C0 0000 17C0 0000 17C0 0000 17C0 0000 17C0 0000 17C0 0000 17C0 0000 17C0 ALTERNATE 0000 005F 0000 005F 0000 005F 0000 005F 0000 005F 0000 005F 0000 005F 0000 005F 0000 005F 16 BITS FFC0 1780 F700 0ec0 F6C0 0E80 F680 0E40 F640 0E00 F600 0DC0 F5C0 0D80 F580 0D40 F540 0D00 RESHI:RESLO ALTERNATE FFFF 005E FFDC 003B FFDB 003A FFDA 0039 FFD9 0038 FFD8 0037 FFD7 0036 FFD6 0035 FFD5 0034
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PECI-to-I2C Translator
data (with the exception of error codes) and the relative temperatures are listed for reference only. Table 12 shows the values with 16-bit and alternate word format. The read maximum temperature command from Table 11 returns the highest temperature that is not an error code from the enabled PECI sockets and domains. This operation works on signed numbers only and does not give information as to what socket the temperature result comes from. To find the socket and domain, use the read maximum temperature address command as shown in Table 13.
MAX6621
DATA FROM PECI
Y
ERROR?
N
AVERAGING
Table 13. Read Maximum Temperature Address
COMMAND 0Ah DESCRIPTION Read address of socket/domain with the maximum temperature TYPE ReadWord RESULT
N
ALT. FORMAT?
Y
16-bit
CONVERT DATA FORMAT
The read maximum temperature address command returns the register that had the highest temperature when read maximum temperature was last called. An error is returned if the read maximum temperature has not been called or when the read maximum temperature itself returns an error.
ADD OFFSET
RETURN DATA ON I2C
Return Value Flow Chart Figure 4 shows the operations performed on temperature data read through PECI.
Figure 4. Operational Flowchart
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PECI-to-I2C Translator MAX6621
Error Codes
Error codes are represented as 16-bit words in the 8000h-81FFh range as shown in Table 14.
Table 15. Read/Write Temperature Alert Commands
COMMAND DESCRIPTION Read/write alert temperature for socket 0 Read/write alert temperature for socket 1 Read/write alert temperature for socket 2 Read/write alert temperature for socket 3 TYPE ReadWord/ WriteWord DEFAULT 7FFFh
Table 14. Error Codes
ERROR CODES 8000h- 80FFh 8100h 8101h 8102h 10h DESCRIPTION Refer to Intel PECI specification. PECI transaction failed for more than the configured number of consecutive retries. Polling disabled for requested socket/domain. First poll not yet completed for requested socket/domain (on startup). Read maximum temperature requested, but no sockets/domains enabled or all enabled sockets/domains have errors; or read maximum temperature address requested, but read maximum temperature was not called. Get alert socket/domain requested, but no alert active. 13h 12h
11h
ReadWord/ WriteWord
7FFFh
ReadWord/ WriteWord
7FFFh
ReadWord/ WriteWord
7FFFh
8103h
8104h
ALERT Output
The MAX6621 asserts ALERT when a PECI temperature exceeds a configurable threshold after averaging. Table 15 below shows the registers that set the threshold and read the alert temperature for each socket. If there are no active alerts, an error is returned as shown in Table 14. If polling is disabled, the alert temperatures are only checked when the request polling command is called. Once ALERT is asserted, a subsequent drop in temperature does not clear the alert. ALERT must be cleared by calling the clear alert command.
Clear Alert The clear alert is shown in Table 16, and this command clears an active alert. If the temperature still exceeds one of the thresholds after clearing, ALERT reasserts on the next PECI temperature read. New alerts are disabled when mask alerts (CONFIG0, bit 4) is set. This does not affect an existing alert. The clear alert command needs to be called to clear it.
Table 16. Clear Alert
COMMAND 15h DESCRIPTION Clear alert TYPE SendByte
Read Alert Socket/Domain Table 17 shows the read alert socket/domain command. Call this command to check for the socket/ domain (register) that caused the alert to become active. If multiple temperatures exceed their respective thresholds, only the first violation is recorded. Register address is held in low byte.
Table 17. Read Alert Socket/Domain
COMMAND 0Bh DESCRIPTION Read alert socket and domain TYPE ReadWord RESULT 16-bit word
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PECI-to-I2C Translator
The result is a 16-bit word (low byte transmitted first, high byte second) that contains the register that caused ALERT to assert. An error (8103h) is returned when there is no active ALERT. The result is a 16-bit word (low byte transmitted first, high byte second), e.g., 0100h for the MAX6621 firmware version 1.0.
MAX6621
RESET
The MAX6621 features a power-on reset (POR), bus lockout reset, and a reset input (RESET). The power-on reset monitors VCC and holds all outputs in high impedance until V CC passes the POR threshold. The MAX6621 monitors VCC for brownout conditions even after power-up.
Serial Interface
The MAX6621 operates as a slave that sends and receives data through an I2C-compatible, 2-wire interface. The interface uses a serial-data line (SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master and slave. A master (typically a microcontroller) initiates all data transfers to and from the MAX6621 and generates the SCL clock that synchronizes the data transfer (Figure 5). The MAX6621 SCL and SDA lines operate as both inputs and open-drain outputs. A pullup resistor is required on SCL and SDA. Each transmission consists of a START condition sent by a master, followed by the MAX6621 7-bit slave address, plus an R/W bit, one or more data bytes, and finally a STOP condition (Figure 6). To write to a MAX6621 register, a write transmission consists of a START condition, followed by the MAX6621 7-bit slave address plus R/W = 0, a register address byte, one data byte, and finally a STOP condition. To read from a MAX6621 register, a combined write and read transmissions are required. The first write transmission consists of a START condition, followed by the MAX6621 7-bit slave address plus R/W = 0, a register address byte, and finally a STOP condition that sets the register to be read. The second read transmission consists of a START condition, followed by the MAX6621 7-bit slave address plus R/W = 1, one or more data bytes, and finally a STOP condition that reads the data from the
Bus Lockout Timeout Reset If an I 2 C transaction starts and gets locked up for greater than 20ms, the MAX6621 asserts the internal bus lockup reset that restarts itself in the default startup condition.
RESET Input The MAX6621 features a RESET input that allows users to directly reset to the default startup conditions. Pull RESET low for a minimum of 10ns for a valid reset. The MAX6621 requires 100s to be accessible after RESET has been asserted.
Version Information Command
Table 18 shows the command to read the firmware version.
Table 18. Firmware Command
COMMAND 09h DESCRIPTION Get firmware version TYPE ReadWord RESULT 16 bit word
SDA tSU, DAT tLOW SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tSU, STO tBUF
Figure 5. 2-Wire Serial-Interface Timing Details
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PECI-to-I2C Translator MAX6621
specified register. These write and read transmissions can be joined using a repeated START even though the MAX6621 7-bit slave address needs to be present preceding the R/W bits. The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (Figure 8). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse so that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX6621, the MAX6621 generates the acknowledge bit because the MAX6621 is the recipient. When the MAX6621 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient.
Start and Stop Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 6).
SDA
START CONDITION SCL SDA BY TRANSMITTER SDA BY RECEIVER S 1 2
CLOCK PULSE FOR ACKNOWLEDGEMENT 8 9
SCL
S START CONDITION
P STOP CONDITION
Figure 8. Acknowledge Figure 6. Start and Stop Conditions
Data Transfer and Acknowledge One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 7).
Slave Address The MAX6621 has a 7-bit long slave address (Figure 9). The 8th bit following the 7-bit slave address is the R/W bit. The R/W bit is low for a write command and high for a read command.
SDA
SDA
SCL
1 MSB
0
0
1
0
A1
A0
R/W LSB
ACK
SCL
DATA LINE STABLE; CHANGE OF DATA DATA VALID ALLOWED
Figure 7. Bit Transfer
Figure 9. Slave Address
14
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PECI-to-I2C Translator
The first 5 bits of the MAX6621 slave address (A6-A2) are always 1, 0, 0, 1, and 0. The MAX6621 slave address bit A1 is set during the manufacturing process and A0 is selected by the address input AD0. AD0 can be connected to GND or VCC. The MAX6621 has two possible slave addresses selectable by AD0, and a total of four addresses available by factory programming the value of A1. Therefore, a maximum of four MAX6621 devices can be controlled independently from the same interface (see the I2C Address Range section).
MAX6621
TYPICAL READ WORD COMMAND PEC (PACKET ERROR CHECKSUM) ENABLED MASTER MAX6621 ADDR:7 ADDR:7 W R A A CMD:8 RESLO:8 A A RESHI:8 A PEC:8 NA P
PEC (PACKET ERROR CHECKSUM) DISABLED MASTER MAX6621 ADDR:7 ADDR:7 W R A A CMD:8 RESLO:8 A A RESHI:8 NA P
TYPICAL WRITE WORD COMMAND COMMAND WITH PEC (PACKET ERROR CHECKSUM) MASTER S ADDR:7 W A CMD:8 A INLO:8 A INHI:8 A PEC:8 A P
COMMAND WITHOUT PEC (PACKET ERROR CHECKSUM) MASTER S ADDR:7 W A CMD:8 A INLO:8 A INHI:8 A P
THE RESULT CONSISTS OF RESLO FOR THE 8 LEAST SIGNIFICANT BITS (LSBS) AND RESHI FOR THE 8 MOST SIGNIFICANT BITS (MSBS), RESULTING IN A 16-BIT WORD. TEMPERATURE DATA AND ERROR CODES ARE GIVEN AS 16-BIT WORDS. ADDR:7: 7-BIT ADDRESS FOLLOWED BY A READ (R = 1) OR WRITE (W = 0) BIT TO FORM THE 8-BIT ADDRESS USED IN THE I2C/SMBUS PROTOCOL. P: I2C STOP CONDITION. SEE FIGURE 6. S: I2C START CONDITION. SEE FIGURE 6. A: ACK. THE PULSE ON THE 9th CLOCK CYCLE TO INDICATE ACKNOWLEDGE TRANSFER. SLAVE PULLS LOW TO GND AND MASTER PULLS TO SLAVE'S VOL. NA: NOT ACKNOWLEDGE CMD: COMMAND BYTE RESLO: LEAST SIGNIFICANT 8-BIT RESULT RESHI: MOST SIGNIFICANT 8-BIT RESULT
Figure 10. Typical Read/Write Word Command
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15
PECI-to-I2C Translator
Message Format for Writing to the MAX6621 A write to the MAX6621 consists of the transmission of the MAX6621's slave address with the R/W bit set to zero, followed by at least 1 byte of information. The first byte of information is the command byte. The command byte determines which register of the MAX6621 is to be written to by the next byte or read from during the next read transmission. If a STOP condition is detected after the command byte is received, the MAX6621 takes no further action beyond setting the register address. The bytes received after the command byte are data bytes. The data bytes go into the register of the MAX6621 specified by the command byte. Only the last data byte or word transmitted before a STOP condition is stored by the device (Figure 10). Message Format for Reading the MAX6621 The MAX6621 is read using the MAX6621's internally stored command byte as an address pointer the same way the stored command byte is used as an address pointer for a write. The pointer autoincrements after each data byte is read. Thus, a read is initiated by first configuring the MAX6621's command byte by performing a write. The master can now read N consecutive bytes from the MAX6621 with the first data byte being read from the register addressed by the initialized command byte (Figure 10).
MAX6621
bus after master 1 has set up the MAX6621's address pointer, but before master 1 has read the data. If master 2 subsequently changes the MAX6621's address pointer, master 1's delayed read can be from an unexpected location. The use of multiple masters is not recommended.
I2C Address Range The I2C device address is configurable using address inputs AD0 and A1. Using the address inputs A0 and A1, the base address can be configured from 48h to 4Bh (Table 19).
Table 19. MAX6621 Slave Addresses
10010: A1:A0 0:0 0:1 1:0 1:1 I2C ADDRESS 48h 49h 4Ah 4Bh I2C ADDRESS INCLUDING R/W BIT 90h, 91h 92h, 93h 94h, 95h, A1 = 1 is a factory option 96h, 97h, A1 = 1 is a factory option
Choosing Pullup Resistors
I2C requires pullup resistors to provide a logic-high level to data and clock lines. There are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I2C specifies a minimum 300ns rise time to go from low to high (30% to 70%) for fast mode, which is defined for a date rate of 400kbps (refer to the I2C specifications for details). To meet the rise time requirement, choose pullup resistors so that the rise time tR = 0.85RPULLUP x CBUS < 300ns. For typical low bus capacitances, a 4.7k resistor can be used. For a bus capacitance of 400pF, choose a pullup resistor less than 880. Many I2C devices work when the minimum specified rise time is not met. However, if the time it takes for the waveform to rise becomes too slow, these waveforms are not recognized by the master.
Packet Error Checksum (PEC)
All MAX6621 I2C packets have an optional packet error checksum (PEC). The PEC is implemented in accordance with the SMBus specification, versions 1.1 and 2. The MAX6621 accepts commands with or without PEC. The PEC for device responses is optional and can be disabled in the CONFIG0 register.
Applications Information
Operation with Multiple Masters
If the MAX6621 is operated on a 2-wire interface with multiple masters, a master reading the MAX6621 should use a repeated START between the write that sets the MAX6621's address pointer, and the read(s) that takes the data from the location(s) (Table 19). This is because it is possible for master 2 to take over the
16
______________________________________________________________________________________
PECI-to-I2C Translator
Pin Configuration
PROCESS: CMOS
TOP VIEW
PECI 1 AGND AD0 SDA SCL 2 3 4 5
Chip Information
MAX6621
+
10 VREF 9 ALERT RESET GND VCC
MAX6621
8 7 6
MAX
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17
PECI-to-I2C Translator MAX6621
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 0.120 E1 0.116 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF 0.0106 b 0.007 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H
O0.500.1
0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Heaney

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